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abcu-57xxxxz family 10/100/1000base-t 1.25 gbd small form pluggable low voltage (3.3 v) electrical transceiver over category 5 cable data sheet description the abcu-57xxxxz family of electrical transceivers from avago technologies ofer full-duplex throughput of 1000 mbps by transporting data over shielded and unshielded twisted pair category 5 cable with 5-level pam (pulse amplitude modulation) signals. the avago technologies 1000base-t module takes sig - nals from both the twisted pair category 5 cable and the serdes interface. pin count overhead between the mac and the phy is minimized, and gigabit ethernet opera - tion is achieved with maximum space savings. product ordering information abcu-5730rz -5~70 rx_los enabled abcu-5740rz -5~70 rx_los disabled ABCU-5730GZ -5~70 rx_los enabled & isolated ground abcu-5730arz -40~85 rx_los enabled abcu-5740arz -40~85 rx_los disabled abcu- 5740agz -40~85 rx_los disabled & isolated ground abcu-5731arz -40~85 sgmii rx_los enabled abcu-5741arz -40~85 sgmii rx_los disabled abcu-5741agz -40~85 sgmii rx_los disabled & isolated ground abcu-5731rz -5~70 sgmii rx_los enabled abcu-5741rz -5~70 sgmii rx_los disabled related products afbr-5710z family of 850nm +3.3v sfp optical transceivers for gigabit ethernet afct-5710z family of 1310nm +3.3v sfp optical transceivers for gigabit ethernet features ? rohs-6 compliant (see table 1) ? designed for industry-standard, small form factor pluggable (sfp) ports ? compliance with ieee 802.3:2005 ? custom rj-45 connector with integrated magnetics ? link lengths at 1.25 gbd: up to 100 m per ieee802.3 ? low power, high performance 1.25 gbd serdes inte - grated in module ? single +3.3 v power supply operation ? auto-negotiation per ieee 802.3:2005 clause 28 (twisted pair) and clause 37 (1000base-x) ? compatible to both shielded and unshielded twisted pair category 5 cable ? available in commercial temperature (-5~70 c) and industrial temperature (-40~85 c) ? 10/100/1000base-t operation available with sgmii host systems. applications ? switch to switch interface ? switched backplane applications ? file server interface module diagrams figure 1 illustrates the major functional components of the abcu-57xxxxz family of transceivers. the 20-pin connection diagram of module printed circuit board of the module is shown in figure 2. figure 3 depicts the pin assignment of the mdi (rj45 jack). figure 6 depicts the external confguration and dimen - sions of the module.
2 figure 3. mdi ( rj 45 jack) pin assignment magnetics rj45 adapter eeprom serdes/ dsp tx_data rx_data tx_disable rx_los mod_def2 mod_def1 mod_def0 100 100 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 2 3 4 5 6 7 8 9 1 0 v e e t t d - t d + v e e t v c c t v c c r v e e r r d + r d - v e e r v e e t t x _ f a u l t t x _ d i s a b l e m o d - d e f ( 2 ) m o d - d e f ( 1 ) m o d - d e f ( 0 ) r at e s el ec t l o s v e e r v e e r t o p o f b o ar d b o t t o m o f b o ar d ( as v i ew ed t h r u t o p o f b o ar d ) pin 1 pin 8 note: los is only applicable for abcu-573xxxz models figure 2. 20-pin connection diagram of module printed circuit board serial identifcation (eeprom) the abcu-57xxxxz family complies with an industry stan - dard multisource agreement that defnes the serial identi - fcation protocol. this protocol uses the 2-wire serial cmos eeprom protocol of the atmel at24c01a or equivalent. the contents of the abcu-57xxxxz family serial id memory are defned in table 10 as specifed in the sfp msa. controller and data i/o data i/os are designed to accept industry standard dif - ferential signals. in order to reduce the number of passive components required on the customers board, avago technologies has included the functionality of the trans - mitter bias resistors and coupling capacitors within the module. the transceiver is compatible with an ac-coupled confguration and is internally terminated. figure 1 depicts the functional diagram of the abcu-57xxxxz family of transceivers. 100-ohm resistor shown at rx_los in figure 1 refers to abcu-573xxxz confguration. caution should be taken into account for the proper inter - connection between the supporting physical layer integrat - ed circuits and the abcu-57xxxxz family of transceivers. figure 4 illustrates the recommended interface circuit. several control data signals and timing diagrams are imple - mented in the module and are depicted in figure 6. installation the abcu-57xxxxz family can be installed in or removed from any multisource agreement (msa) compliant small form pluggable port whether the host equipment is operating or not. the module is simply inserted, small end frst, under fnger-pressure. controlled hot-plugging is ensured by design and by 3-stage pin sequencing at the electrical interface to the host board. the module housing makes initial contact with the host board emi shield, mitigating potential damage due to electrostatic discharge (esd). the module pins sequentially contact the (1) ground, (2) power, and (3) signal pins of the host board surface mount connector. this printed circuit board card-edge connector is depicted in figure 2. figure 1. transceiver functional diagram
3 protocol ic serdes v_supply tx[0:9] rx[0:9] 10 uf 0.1 uf 1 uh 1 uh 0.1 uf 10 uf 0.1 uf vcc_t vcc_r 4.7 k tx_disable tx_fault td+ td- rd+ rd- 100 rx_los ref clk v_supply mod_def 1 mod_def 2 mod_def 0 4.7 k 4.7 k 4.7 k 4.7 k 0.01 uf abcu-57xxxxz eeprom rj45 jack & magnetics cat5 cable 0.01 uf 0.01 uf 0.01 uf phy ic 100 100 *100 100 100 figure 4. typical application confguration for abcu-57xxxxz v cc t 0.1 f 0.1 f 10 f 1 h 1 h 0.1 f 10 f 3.3 v sfp module v cc r host board note: inductors must have less than 1ohm series resistance per msa figure 5. msa recommended power supply filter * all models that have los disabled, will ground the los pin through a 100 ohm internal resistor.
4 table 1. regulatory compliance feature test method performance electrostatic discharge (esd) to the electrical pins mil-std-883c method 3015.4 jedec/eia jes022-a114-a class 2 (2000 volts) electrostatic discharge (esd) to the rj 45 connector receptacle variation of iec 61000-4-2 typically withstand 15 kv ( air discharge), 8 kv (contact) without damage when the rj 45 connector receptacle is contacted by a human body model probe. electromagnetic interference (emi) fcc part 15 class b cenelec en55022 class b (cispr 22a)vcci class 1 system margins are dependent on customer board and chassis design. radiated immunity variation of iec 61000-4-3 typically shows a negligible efect from a 10 v/m feld swept from 80 to 1000 mhz applied to the transceiver without a chassis enclosure. component recognition underwriters laboratories and canadian standards association joint component recognition for information technology equipment including electrical business equipment ul file # e173874 grounding confguration dc short between signal and chassis grounds - meets all regulatory requirements as listed above. - compliant with system boards using multi-point grounding scheme rohs compliance chemical composition analysis less than 0.1% lead, mercury, hexavalent chromium, polybrominated biphenyls, and polybrominated biphenyl ethers by weight of homogeneous material. exemption for lead in high melting temperature solder applied to module connector. less than 0.01% cadmium by weight of homogeneous material. application support evaluation kit to help you in your preliminary transceiver evaluation, avago technologies ofers a 1.25 gbd gigabit ethernet evaluation board. this board will allow testing of the electrical parameters of transceiver. please contact your local field sales representative for availability and order - ing details. regulatory compliance see table 1 for transceiver regulatory compliance perfor - mance. the overall equipment design will determine the certifcation level. the transceiver performance is ofered as a fgure of merit to assist the designer. immunity equipment hosting the abcu-57xxxxz modules will be subjected to radio-frequency electromagnetic felds in some environments. the transceivers have excellent im - munity to such felds due to their shielded design. electrostatic discharge (esd) there are two conditions in which immunity to esd dam - age is important. table 1 documents our immunity to both of these conditions. the frst condition is during han - dling of the transceiver prior to insertion into the trans - ceiver port. to protect the transceiver, it is important to use normal esd handling precautions. these precautions include using grounded wrist straps, work benches, and foor mats in esd controlled areas. the esd sensitivity of the abcu-57xxxxz is compatible with typical industry production environments. the second condition is static discharges to the exterior of the host equipment chassis after installation. to the extent that the rj45 connector interface is exposed to the outside of the host equipment chassis, it may be subject to system-level esd requirements. the esd performance of the abcu-57xxxxz exceeds typical industry standards.
5 electromagnetic interference (emi) most equipment designs utilizing these high-speed trans - ceivers from avago technologies will be required to meet the requirements of fcc in the united states, cenelec en55022 (cispr 22a) in europe and vcci in japan. the metal housing and shielded design minimize the emi challenge facing the host equipment designer. these transceivers provide superior emi performance. this greatly assists the designer in the management of the overall system emi performance. flammability the abcu-57xxxxz electrical transceiver housing is made of metal and high strength, heat resistant, chemi - cally resistant, and ul 94v-0 fame retardant plastic. caution there are no user serviceable parts nor any maintenance required for the abcu-57xxxxz. tampering with or modifying the performance will result in voided product warranty. it may also result in improper operation of the abcu-57xxxxz circuitry, and possible overstress of the rj 45 connector. device degradation or product failure may result. connecting the module to a non-approved 1000baset module, operating above the recommended absolute maximum conditions or operating the abcu- 57xxxxz in a manner inconsistent with its design and function may result in hazardous radiation exposure and may be considered an act of modifying or manufacturing an electrical module product. ordering information please contact your local feld sales engineer or one of avago technologies franchised distributors for ordering information. for technical information, please visit avago technologies web page at www.avagotech.com or con - tact avago technologies customer response center. for information related to the msa visit www.schelto.com/ sfp/index.html customer manufacturing processes this module is pluggable and is not designed for aqueous wash, ir refow or wave soldering processes.
6 table 2. 20-pin connection diagram description pin name function/description msa notes 1 v ee t transmitter ground 2 tx fault transmitter fault indication - high indicates a fault note 1 3 tx disable transmitter disable - module disables on high or open note 2 4 mod-def2 module defnition 2 - two wire serial id interface note 3 5 mod-def1 module defnition 1 - two wire serial id interface note 3 6 mod-def0 module defnition 0 - grounded in module note 3 7 rate select not connected 8 los loss of signal - high indicates loss of signal note 4 9 v ee r receiver ground 10 v ee r receiver ground 11 v ee r receiver ground 12 rd- inverse received data out note 5 13 rd+ received data out note 5 14 v ee r receiver ground 15 v cc r receiver power - 3.3 v +/- 5% note 6 16 v cc t transmitter power - 3.3 v +/- 5% note 6 17 v ee t transmitter ground 18 td+ transmitter data in note 7 19 td- inverse transmitter data in note 7 20 v ee t transmitter ground notes: 1. tx fault is not used and is always tied to ground through a 100 ohm resistor. 2. tx disable as described in the msa is not applicable to the 1000base-t module, but is used for convenience as an input to reset the internal asic. this pin is pulled up within the module with a 4.7 k w resistor. low (0 C 0.8 v): transceiver on between (0.8 v and 2.0 v): undefned high (2.0 C 3.465 v): transceiver in reset state open: transceiver in reset state 3. mod-def 0,1,2. these are the module defnition pins. they should be pulled up with a 4.7-10 k w resistor on the host board to a supply less than v cc t + 0.3 v or v cc r + 0.3 v. mod def 0 is tied to ground through a 100 ohm resistor to indicate that the module is present. mod-def 1 is clock line of two wire serial interface for optional serial id mod-def 2 is data line of two wire serial interface for optional serial id 4. los (loss of signal) operation on the 1000baset sfp is diferent than for optical sfp applications. for models with rx_los enabled, rx_los signal is a 1000base-t linkup/link-down indicator and not a peak (ac) or voltage (dc) detector. for models where rx_los is disabled, rx_los is not used and is always tied to ground via 100-ohm resistor. 5. rd-/+: these are the diferential receiver outputs. they are ac coupled 100 w diferential lines which should be terminated with 100 w diferential at the user serdes. the ac coupling is done inside the module and is thus not required on the host board. the voltage swing on these lines will be between 370 and 2000 mv diferential (185 C 1000 mv single ended) when properly terminated. these levels are compatible with cml and lvpecl voltage swings. 6. v cc r and v cc t are the receiver and transmitter power supplies. they are defned as 3.3 v 5% at the sfp connector pin. the maximum supply current is 317 ma and the associated in-rush current will typically be no more than 30 ma above steady state after 500 nanoseconds. 7. td-/+: these are the diferential transmitter inputs. they are ac coupled diferential lines with 100 w diferential termination inside the module. the ac coupling is done inside the module and is thus not required on the host board. the inputs will accept diferential swings of 500 C 2400 mv (250 C 1200 mv single ended), though it is recommended that values between 500 and 1200 mv diferential (250 C 600 mv single ended) be used for best emi performance. these levels are compatible with cml and lvpecl voltage swings.
7 absolute maximum ratings parameter symbol minimum typical maximum unit notes storage temperature t s -40 +85 c note 1 case temperature t c -40 +85 c note 1 ,2 relative humidity rh 5 95 % note 1 module supply voltage v cc t,r -0.5 3.6 v note 1, 2 data/control input voltage v i -0.5 v cc v note 1 sense output current - mod-def2 5.0 ma recommended operating conditions parameter symbol minimum typical maximum unit notes case temperature t c -5 -40 70 85 c c note 3 module supply voltage v cc t,r 3.135 3.3 3.465 v note 3 data rate 1.25 gb/s note 3 transceiver electrical characteristics (t c = -5 c to +70 c, v cc t,r = 3.3 v 5%) (tc = -40 c to +85c, vcct,r = 3.3 v +/- 5%) parameter symbol minimum typical maximum unit notes ac electrical characteristics power supply noise rejection (peak-peak) psnr 100 mv note 4 dc electrical characteristics module supply current (t c = -5 c to +70 c, v cc t,r = 3.3 v 5%) (tc = -40 c to +85c, vcct,r = 3.3 v +/- 5%) i cc 350 370 ma power dissipation (t c = -5 c to +70 c, v cc t,r = 3.3 v 5%) (tc = -40 c to +85c, vcct,r = 3.3 v +/- 5%) p diss 1100 1150 mw sense outputs: mod-def2 rx_los v oh 2.0 v cc t, r+ 0.3 v note 5 v ol 0 0.4 control inputs: transmitter disable(tx_disable), mod-def1, 2 v ih 2.0 v cc v note 5 v il 0 0.8 v notes: 1. absolute maximum ratings are those values beyond which damage to the device may occur if these limits are exceeded for other than a short period of time. see reliability data sheet for specifc reliability performance. 2. between absolute maximum ratings and the recommended operating conditions functional performance is not intended, device reliability is not implied, and damage to the device may occur over an extended period of time. 3. operating conditions will vary, depending on model. recommended operating conditions are those values outside of which functional perfor - mance is not intended, device reliability is not implied, and damage to the device may occur over an extended period of time. see reliability data sheet for specifc reliability performance later when it is ready. 4. msa-specifed flter is required on the host board to achieve psnr performance over the frequency range 10 hz to 2 mhz. 5. lvttl, external 4.7-10 k w pull-up resistor required for mod-def 1 and mod-def 2.
8 transmitter and receiver electrical characteristics (t c = -5 c to +70 c, v cc t,r = 3.3 v 5%) (tc = -40 c to +85c, vcct,r = 3.3 v +/- 5%) parameter symbol minimum typical maximum unit notes data input: transmitter diferential input voltage (td +/-) v i 500 2400 mv note 1 data output : receiver diferential output voltage (rd +/-) v o 370 735 2000 mv note 2 receive data rise & fall times (receiver) trf 100 250 ps note 3 transceiver timing characteristics (t c = -5 c to +70 c, v cc t,r = 3.3 v 5%) (tc = -40 c to +85c, vcct,r = 3.3 v +/- 5%) parameter symbol minimum typical maximum unit notes tx disable assert time t_of na note 4 tx disable negate time t_on na note 4 module reset assert time t_of_rst 10 m s note 5 module reset negate time t_on_rst 300 ms note 6 time to initialize t_init 300 ms tx fault assert time t_fault na note 7 tx disable to reset t_reset na note 7 los assert time t_loss_on na note 7 los de-assert time t_loss_of na note 7 rate select change time t_ratesel na note 7 serial id clock rate f_serial_clock 100 khz notes: 1. internally ac coupled and terminated (100 ohm diferential). these levels are compatible with cml and lvpecl voltage swings. 2. internally ac coupled with an external 100 ohm diferential load termination. 3. 20%-80% rise and fall times measured with a 500 mhz signal utilizing a 1010 pattern. 4. tx disable function as described in the sfp msa is not used in the 1000base-t module. 5. time from rising edge of tx disable until link comes down. 6. time from falling edge of tx disable until auto-negotiation starts. 7. not used in the 1000base-t module
9 figure 6. transceiver timing diagrams (module installed except where noted) v cc > 3.15 v t_init power saving (tx_disable) transmitted signal (auto-negotiation begins) t-init: module hot-plugged or voltage applied after insertion, when tx_disable is negated v cc > 3.15 v t_init tx_disable transmitted signal (auto-negotiation begins) t-init: voltage applied when tx_disable is asserted t_on_rst t_o_rst tx_disable transmitted signal (auto-negotiation begins on rising edge) t_o_rst & t_on_rst: tx_disable (reset) asserted then de-asserted t_on_rst
10 table 3. eeprom serial id memory contents at address a0 addr hex ascii addr hex ascii addr hex ascii addr hex ascii 0 03 40 41 a 68 note 3 96 note 5 1 04 41 42 b 69 note 3 97 note 5 2 00 42 43 c 70 note 3 98 note 5 3 00 43 55 u 71 note 3 99 note 5 4 00 44 2d - 72 note 3 100 note 5 5 00 45 35 5 73 note 3 101 note 5 6 08 46 37 7 74 note 3 102 note 5 7 00 47 note 1 75 note 3 103 note 5 8 00 48 note 1 76 note 3 104 note 5 9 00 49 note 1 77 note 3 105 note 5 10 00 50 note 1 78 note 3 106 note 5 11 01 51 note 1 79 note 3 107 note 5 12 0d 52 20 80 note 3 108 note 5 13 00 53 20 81 note 3 109 note 5 14 00 54 20 82 note 3 110 note 5 15 00 55 20 83 note 3 111 note 5 16 00 56 20 84 note 4 112 note 5 17 00 57 20 85 note 4 113 note 5 18 64 58 20 86 note 4 114 note 5 19 00 59 20 87 note 4 115 note 5 20 41 a 60 00 88 note 4 116 note 5 21 56 v 61 00 89 note 4 117 note 5 22 41 a 62 00 90 note 4 118 note 5 23 47 g 63 note 2 91 note 4 119 note 5 24 4f o 64 00 92 00 120 note 5 25 20 65 note 1 93 00 121 note 5 26 20 66 00 94 00 122 note 5 27 20 67 00 95 note 2 123 note 5 28 20 124 note 5 29 20 125 note 5 30 20 126 note 5 31 20 127 note 5 32 20 33 20 34 20 35 20 36 01 37 00 38 17 39 6a notes: 1. the contents of these registers will change dependent on model number. 2. addresses 63 and 95 are check sums. address 63 is the check sum for bytes 0-62 and address 95 is the check sum for bytes 64-94. 3. address 68-83 specify a unique identifer. 4. address 84-91 specify the date code. 5. these felds are reserved for optional use by avago technologies.
11 table 4. summary of internal ic registers register description 0 control 1 status 2-3 n/a for sfp module 4 auto-negotiation advertisement 5 auto-negotiation link partner ability 6 auto-negotiation expansion 7 auto-negotiation next page transmit 8 auto-negotiation link partner received next page 9 master-slave control register 10 master-slave status register 11-15 n/a for sfp module 16 extended control 1 17 extended status 1 18-19 n/a for sfp module 20 extended control 2 21 receive error counter 22 cable diagnostic 1 23-25 n/a for sfp module 26 extended control 3 27 extended status 2 28 cable diagnostic 2 29-31 n/a for sfp module internal asic registers the asic (or phy, for physical layer ic) in the trans - ceiver module contains 32 registers. each register contains 16 bits. the registers are summarized in table 11 and detailed in table 12 through 28. each bit is either read only (ro) or read/write (r/w). some bits are also described as latch high (lh) or latch low (ll) and/or self clearing (sc). the registers are accessible through the 2-wire se - rial cmos eeprom protocol of the atmel at24c01a or equivalent. the address of the phy is 1010110x, where x is the r/w bit. each registers address is 000yyyyy, where yyyyy is the binary equivalent of the register number. write and read operations must send or receive 16 bits of data, so the multi-page access protocol must be used.
12 table 5. register 0 (control) bit name description hardware reset software reset details 0.15r/w reset 1 = phy reset 0 = normal operation 0 self-clearing performs software reset 0.14r/w loopback 1 = enable 0 = disable 0 0 serial data in on rd+/- is deserial - ized, then reserialized and sent out on td+/- 0.13r/w speed selection (lsb) 0 = 1000 mb/s 0 update paired with bit 0.6. module may function at speeds other than 1000 mb/s depending on model this bit is only meaningful if bit 0.12 is 0. 0.12r/w auto-negotiation enable 1 = enable 0 = disable 1 update changes to this bit take efect after software reset. 0.11r/w power down 1 = power down 0 = normal operation 0 0 0.10r/w isolate 1 = isolate 0 = normal operation 0 0 0.9r/w/sc restart auto- negotiation 1 = restart auto-nego - tiation process 0 = normal operation 0 self-clearing 0.8r/w duplex mode 1 = full duplex 0 = half duplex 1 update this bit is only meaningful if 0.12 is 0. 0.7r/w collision test 1 = enable col signal test 0 = disable col signal test 0 0 0.6r/w speed selection (msb) 1 = 1000 mb/s 1 update paired with bit 0.13. module may function at speeds other than 1000 mb/s depending on model this bit is only meaningful if bit 0.12 is 0. 0.5:0r/w n/a to sfp module 000000 000000
13 table 6. register 1 (status) bit name description hardware reset software reset details 1.15:9 ro n/a to sfp module 0000000 0000000 1.8 ro extended status 1 = extended status information in register 15 1 1 always 1 1.7 ro n/a to sfp module 0 0 1.6 ro mf preamble suppression 1 = phy will accept management frames with preamble suppressed. 1 1 always 1 1.5 ro auto-negotiation complete 1 = auto-negotiation process completed 0 = auto-negotiation process not com - pleted 0 0 1.4 ro/lh remote fault 1 = remote fault condition detected 0 - no remote fault condition detected 0 0 1.3 ro auto-negotiation ability 1 = module is able to perform auto-nego - tiation 0 = module is unable to perform auto- negotiation 1 1 1.2 ro/ll link status 1 = link is up 0 = link is down 0 0 1.1 ro/lh jabber detect 1 = jabber condition detected 0 = no jabber condition detected 0 0 1.0 ro extended capability 1 = extended register capabilities 1 1 always 1
14 table 7. register 4 (auto-negotiation advertisement) bit name description hardware reset software reset details 4.15:14 r/w n/a to sfp module 10 10 when writing to register 4, be sure to preserve the values of these bits. changes to these values can interrupt the normal operation of the sfp module. 4.13 r/w remote fault 1 = remote fault bit is set 0 = no remote fault 0 retain this bit takes efect after auto- negotiation is restarted, either via bit 0.9 or because the link goes down. 4.12 r/w n/a to sfp module 0 retain 4.11:10 r/w pause encoding 11 = both asymmetric pause and symmetric pause toward local device 10 = asymmetric pause toward link partner 01 = symmetric pause 00 = no pause 00 retain this bit takes efect after auto- negotiation is restarted, either via bit 0.9 or because the link goes down. 4.9 r/w n/a to sfp module 0 0 4.8 r/w 100base-tx full duplex 1 = advertise phy is 100base-tx full duplex capable 0 = advertise phy is not 100base-tx full duplex capable 1 (for abcu- 57x1-xxx) 0 (for abcu- 57x0-xxx) retain this bit takes efect auto-negoti - ation is restarted via bit 0.9 4.7 r/w 100base-tx half duplex 1 = advertise phy is 100base-tx half duplex capable 0 = advertise phy is not 100base-tx half duplex capable 1 (for abcu- 57x1-xxx) 0 (for abcu- 57x0-xxx) retain this bit takes efect auto-negoti - ation is restarted via bit 0.9 4.6 r/w 10base-t full- duplex 1 = advertise phy is 10base-t full duplex capable 0 = advertise phy is not 10base-t full duplex capable 1 (for abcu- 57x1-xxx) 0 (for abcu- 57x0-xxx) retain this bit takes efect auto-negoti - ation is restarted via bit 0.9 4.5 r/w 10base-t half- duplex 1 = advertise phy is 10base-t half duplex capable 0 = advertise phy is not 10base-t half duplex capable 1 (for abcu- 57x1-xxx) 0 (for abcu- 57x0-xxx) retain this bit takes efect auto-negoti - ation is restarted via bit 0.9 4.4:0 ro ieee 802.3 selector field 00001 00001 set per ieee standard.
15 table 8. register 5 (auto-negotiation link partner ability) bit name description hardware reset software reset details 5.15 ro next page 1 = link partner advertises next page ability 0 = link partner does not advertise next page ability 0 0 5.14 ro acknowledge 1 = link partner acknowledges receiv - ing link code word from module 0 = link partner does not acknowledge receiving link code word from module 0 0 5.13 ro remote fault 1 = link partner has a remote fault 0 = link partner does not have a remote fault 0 0 5.12 ro n/a to sfp module 0 0 5.11:10 ro pause encoding 11 = asymmetric pause and symmetric pause toward local device 10 = asymmetric pause toward link partner 01 = symmetric pause 00 = no pause 00 00 5.9:5 ro n/a to sfp module 00000 00000 5.4:0 ro ieee 802.3 selector field 00000 00000 set per ieee standard. table 9. register 6 (auto-negotiation expansion) bit name description hardware reset software reset details 6.15:5 ro n/a to sfp module 00000000000 00000000000 6.4 ro parallel detection fault 1 = a fault has been detected via the parallel detection function 0 = a fault has not been detected via the parallel detection function 0 0 this register is not valid until auto- negotiation is com - plete, as indicated by bit 1.5. 6.3 ro link partner next page able 1 = link partner is next page able 0 = link partner is not next page able 0 0 see note in bit 6.4. 6.2 ro next page able 1 = local device is next page able 0 = local device is not next page able 1 1 see note in bit 6.4. 6.1 ro/lh page received 1 = a new page has been received 0 = a new page has not been received 0 0 see note in bit 6.4. 6.0 ro link partner auto- negotiation able 1 = link partner is auto-negotia - tion able 0 = link partner is not auto-nego - tiation able 0 0 see note in bit 6.4.
16 table 10. register 7 (auto-negotiation next page transmit register) bit name description hardware reset software reset details 7.15 r/w next page 1 = additional next pages to follow 0 = last page 0 0 7.14 ro n/a to sfp module 0 0 7.13 r/w message page 1 = message page 0 = unformatted page 1 1 7.12 r/w acknowledge 2 1 = will comply with message 0 = will not comply with message 0 0 7.11 ro toggle 1 = previous value of the toggle bit was0 0 = previous value of the toggle bit was 1 0 0 7.10:0 r/w message/unformatted code field 00000000001 00000000001 table 11. register 8 (auto-negotiation link partner received next page) bit name description hardware reset software reset details 8.15 ro next page 1 = additional next pages to follow 0 = last page 0 0 8.14 ro acknowledge 0 0 8.13 ro message page 1 = message page 0 = unformatted page 0 0 8.12 ro acknowledge 2 1 = will comply with mes - sage 0 = will not comply with message 0 0 8.11 ro toggle 1 = previous value of the toggle bit was 0 0 = previous value of the toggle bit was 1 0 0 8.10:0 ro message/unformatted code field 00000000000 00000000000
17 table 12. register 9 (master-slave control) bit name description hardware reset software reset details 9.15:13 r/w transmitter test mode 000 = normal operation 001 = transmit waveform test 010 = transmit jitter test in master mode 011 = transmit jitter test in slave mode 000 000 the module enters test modes when mdi crossover is frst disabled via bits 16.6:5. 9.12 r/w master-slave manual confg enable 1 = enable master-slave manual confguration value in register 9.11 0 = disable master-slave manual confguration value in register 9.11 0 retain this bit takes efect after auto- negotiation is restarted via bit 0.9. 9.11 r/w master-slave confg value 1 = confgure phy as mas - ter during master-slave negotiation 0 = confgure phy as slave during master-slave nego - tiation 1 retain this bit takes efect after auto- negotiation is restarted via bit 0.9. this bit is ignored unless bit 9.12 is 1. 9.10 r/w port type 1 = prefer phy as master (multiport) 0 = prefer phy as slave (single port) 1 retain this bit takes efect after auto- negotiation is restarted via bit 0.9. this bit is ignored unless bit 9.12 is 0. 9.9 r/w 1000base-t full duplex 1 = advertise phy is 1000ba - set-t full duplex capable 0 = advertise phy is not 1000base-t full duplex capable 1 retain this bit takes efect after auto- negotiation is restarted via bit 0.9. 9.8 r/w 1000base-t half duplex 1 = advertise phy is 100base- tx full duplex capable 0 = advertise phy is not 100base-tx full duplex capable 1 (for abcu- 57x1-xxx) 0 (for abcu- 57x0-xxx)0 retain this bit takes efect auto- negotiation is restarted via bit 0.9 9.7:0ro n/a to sfp module 00000000 00000000
18 table 13. register 10 (master-slave status) bit name description hardware reset software reset details 10.15 ro/lh/sc master-slave confguration fault 1 = master-slave con - fguration fault detected 0 = no master-slave confguration fault de - tected 0 0 this bit is cleared each time that this register is read. this bit clears on auto-negotiation enable or auto-negotiation complete. this bit is set if the number of failed master-slave resolutions reaches 7. this bit is set if both phys are forced to master or slave at the same time using bits 9.12 and 9.11. 10.14 ro master-slave confguration resolution 1 = local phy confguration resolved to master 0 = local phy confguration resolved to slave 0 0 10.13 ro local receiver status 1 = local receiver ok 0 = local receiver not ok 0 0 10.12 ro remote receiver status 1 = remote receiver ok 0 = remote receiver not ok 0 0 10.11 ro link partner full duplex 1 = link partner is capable of 1000base-t full duplex 0 = link parnter is not capable of 1000base-t full duplex 0 0 this bit is valid only when the page received bit (6.1) is set to 1. 10.10 ro link partner half duplex 1 = link partner is capable of 1000base-t half duplex 0 = link parnter is not capable of 1000base-t half duplex 0 0 this bit is valid only when the page received bit (6.1) is set to 1. 10.9:8 n/a to sfp module 00 00 10.7:0 ro/sc idle error count counts errors when receiving idle patterns. 00000000 00000000 these bits do not roll over when they are all ones.
19 table 14. register 16 (extended control 1) bit name description hardware reset software reset details 16.15:7 r/w n/a to sfp module 000000000 retain (15:10, 7) or update (9:8) when writing to register 16, be sure to preserve the values of these bits. changes to these values can interrupt the normal operation of the sfp module. 16.6:5 r/w mdi crossover mode 00 = manual mdi confguration 01 = manual mdix confguration 10 = n/a to sfp module 11 = enable automatic crossover 11 update changes to this bit take efect after software reset. 16.4:0 r/w n/a to sfp module 11000 retain (2:0) or update (4:3) when writing to register 16, be sure to preserve the values of these bits. changes to these values can interrupt the normal operation of the sfp module.
20 table 15. register 17 (extended status 1) bit name description hardware reset software reset details 17.15:14 ro speed 10 = 1000 mbps 01 = 100 mbps 00 = 10 mbps 0 retain this bit is only valid after bit 17.11 is set. 17.13 ro duplex 1 = full duplex 0 = half duplex 0 retain this bit is only valid after bit 17.11 is set. 17.12 ro/lh page received 1 = page received 0 = page not received 0 0 17.11 ro speed and duplex resolved 1 = resolved 0 = speed not resolved 0 0 this bit is set when auto-nego - tiation is either completed or disabled. 17.10 ro link 1 = link up 0 = link down 0 0 17.9:7 ro cable length 000 = < 50 m 001 = 50 - 80 m 010 = 80 - 110 m 011 = 110 - 140 m 100 = > 140 m 000 000 17.6 ro mdi crossover status 1 = crossover 0 = no crossover 0 0 crossover means that pairs a+/- (pins 1 & 2 on the rj45 jack) and b+/- (pins 3 & 6) are interchanged and c+/- (pins 4 &5) and d+/- (pins 7 & 8) are interchanged. this bit is only valid after bit 17.11 is set. 17.5:4 ro n/a to sfp module 00 00 17.3 ro mac transmit pause enabled 1 = transmit pause enabled 0 = transmit pause disabled 0 0 this bit refects the capability of the mac to which the module is con - nected on the serial side. this bit is only valid after bit 17.11 is set. 17.2 ro mac receive pause enabled 1 = receive pause enabled 0 = receive pause disabled 0 0 this bit refects the capability of the mac to which the module is con - nected on the serial side. this bit is only valid after bit 17.11 is set. 17.1 ro polarity 1 = polarity reversed 0 = polarity not reversed 0 0 this bit is set if any of the four twisted pairs have the + and - wires reversed. 17.0 ro jabber 1 = jabber detected 0 = no jabber detected 0
21 table 16. register 20 (extended control 2) bit name description hardware reset software reset details 20.15 ro link down on no idles 1 = link lock lost 0 = link lock intact 0 0 if idle patterns are not seen within 1 ms, link lock is lost and link is brought down. 20.14:4 r/w n/a to sfp module 00011000110 0001100110 when writing to register 20, be sure to preserve the values of these bits. changes to these values can interrupt the normal operation of the sfp module. 20.3 reserved n/a to sfp module this bit must be read and left r/w unchanged when per - forming a write. 20.2:0r/w n/a to sfp module 000 000 when writing to register 20, be sure to preserve the values of these bits. changes to these values can interrupt the normal operation of the sfp module. table 17. register 21 (receive error counter) bit name description hardware reset software reset details 21.15:0 ro/sc receive errors counts errors received on the 1000base-t side 0 0 these bits do not roll over when they are all ones. table 18. register 22 (cable diagnostic 1) bit name description hardware reset software reset details 22.15:2 ro n/a to sfp module 22.1:0 r/w mdi pair select 00 = pins 1 & 2 (channel a) 01 = pins 3 & 6 (channel b) 10 = pins 4 & 5 (channel c) 11 = pins 7 & 8 (channel d) for vct results, choose the twisted pair on which regis - ter 28 will dsiplay.
22 table 19. register 26 (extended control 3) bit name description hardware reset software reset details 26.15:8 ro n/a to sfp module 00000000 retain 26.7:3 r/w n/a to sfp module 00001 update when writing to register 26, be sure to preserve the values of these bits. changes to these values can interrupt the normal operation of the sfp module. 26.2:0 r/w rd+/- output amplitude 000=0.50v 001=0.60v 010=0.70v 011=0.80v 100=0.90v 101=1.00v 110=1.10v 111=1.20v 010 retain all voltages measured peak-to- peak into a 100-ohm load. table 20. register 27 (extended status 2) bit name description hardware reset software reset details 27.15:13 ro/sc n/a to sfp module 100 update (27.15), retain (27.14:13) when writing to register 27, be sure to preserve the values of these bits. changes to these values can interrupt the normal operation of the sfp module. 27.12 r/w 1000base-x auto-negotiation bypass enable 1 = enabled 0 = disabled 1 update if enabled, base-x link will come up after 200 ms even if base-x auto-negotiation fails. when writing to register 27, be sure to preserve the values of this bit. changes to this value can interrupt the normal operation of the sfp module. 27.11 ro 1000base-x auto-negotiation bypass status 1 = base-x auto-negotia - tion failed and base-x link came up becase bypass mode timer expired 0 = base-x link came up because regular base-x auto-negotiation was completed 0 retain see bit 27.12. 27.10:0 r/w n/a to sfp module 0000001000 (abcu-57x0xxz) 0000000100 (abcu-57x1xxz) update when writing to register 27, be sure to preserve the values of these bits. changes to these values can interrupt the normal operation of the sfp module.
23 table 21. register 28 (cable diagnostic 2) bit name description hardware reset software reset details 28.15 r/w enable cable diagnostic test 1 = enable test 0 = disable test 0 0 the test can only be performed when the link is down. if the link partner is trying to auto-negotiate or if the link partner is sending out idle link pulses, the test will proceed. 28.14:13 ro status 11 = test fail 10 = open detected in twisted pair 01 = short detected in twisted pair 00 = no short or open detected in twisted pair 00 00 the twisted pair under test is specifed in register 22. 28.12:8 ro refected magnitude 11111 = 1 v 10000 = 0 v 00000= -1 v 00000 00000 the twisted pair under test is specifed in register 22. 28.7:0 ro distance distance to the short or open 00000000 00000000 the distance is given in meters by 13/16 * (decimal equivalent of 28.7:0) + 32 .the twisted pair under test is specifed in register 22. if no short or open is detected, these bits are 0s.
24 figure 7. module drawing figure 8. temperature measurement point notes: 1. it is acceptable to measure the temperature of the housing through the label. the label is thin and makes little difference to the temperature measured. 67.9 0.2 13.6 0.1 13.4 0.1 47.50 0.15 8.5 0.1 1 0.10 2.25 0.10 13.95 max. 9.2 0.1 34.6 0.2 41.8 0.15 22.3 0.5 41.5 0.5 25.2 0.5 c l temperature measurement point
for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2014 avago technologies. all rights reserved. obsoletes av01-0165en av02-3410en - march 6, 2014 figure 9. sfp host board mechanical layout

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